This invention relates to semiconductor fabrication processing and, more particularly, to a method for forming polysilicon for semiconductor devices, such as dynamic random access memories (DRAMs).
The continuing trend of scaling down integrated circuits has motivated the semiconductor industry to consider new techniques for fabricating precise components at sub-micron levels. Along with the need for smaller components, there has been a growing demand for devices consuming less power. In the manufacture of memory devices, these trends have led the industry to refine approaches to achieve thinner capacitor cell dielectric and surface enhanced storage capacitor electrodes.
In dynamic random access memory (DRAM) devices it is essential that storage node capacitor cell plates be large enough to exhibit sufficient capacitance in order to retain an adequate charge in spite of parasitic capacitance and noise that may be present during circuit operation. As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. The issue of maintaining storage node capacitance is particularly important as the density of DRAM arrays continues to increase for future generations of memory devices. The ability to densely pack storage cells while maintaining required capacitance levels is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.
One area of manufacturing technology that has emerged has been in the development of Hemi-Spherical Grain (HSG) silicon. HSG silicon enhances storage capacitance when used to form the storage node electrode without increasing the area required for the cell or the storage electrode height. The available methods include use of Low Pressure Chemical Vapor Deposition (LPCVD), engraving storage electrodes using polysilicon film followed by P-diffusion utilizing POCl3 source gas, a mixture of spin-on-glass (SOG), coating the polysilicon with resist, and HSG formation. The size of the silicon grain formed by these processes may be somewhat random and uncontrolled.
The present invention comprises a method to selectively deposit HSG silicon at only desired locations. An exemplary implementation of the present invention comprises a process for selectively forming a silicon structure for a semiconductor assembly. The process first forms a silicon rich material on a semiconductor assembly substrate. Next, a silicon resistive material is formed on the silicon rich material and patterned to allow exposure of a portion of the silicon rich material. Next, a continuous silicon film is formed on the silicon rich material while avoiding the formation of a continuous silicon film on the silicon resistive material. This selective deposition of silicon may be accomplished by presenting a silicon source gas and a silicon stripping agent to the semiconductor assembly. The silicon source gas will readily deposit silicon onto the silicon rich material, while the silicon resistive material will not readily accept the formation of a silicon film thereon. To ensure no continuous silicon is formed on the silicon resistive material, a stripping agent is introduced during the silicon deposition step to remove any silicon nucleation on the silicon resistive film.
A second exemplary implementation of the present invention comprises a process for selectively forming a silicon structure for a semiconductor assembly. The process first forms a conductive silicon rich material on a semiconductor assembly substrate. Next, a nonconductive silicon rich material is formed on the conductive silicon rich material. Next, a silicon reactive material is formed on the nonconductive silicon rich material, where the silicon reactive material and the nonconductive silicon rich material are patterned to expose of a portion of the conductive silicon rich material. Next, a continuous silicon film is formed on the conductive silicon rich material and on the nonconductive silicon rich material while converting the silicon reactive film to a silicon reacted film by presenting a silicon source gas to the semiconductor assembly substrate.